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fn8687 rev 0.00 page 1 of 13 march 2, 2015 fn8687 rev 0.00 march 2, 2015 isl91107ir high efficiency buck-boost r egulator with 4.1a switches datasheet the isl91107ir is a highly-integrated buck-boost switching regulator that accepts input voltages either above or below the regulated output voltage. unlike other buck-boost regulators, this regulator automatically transitions between operating modes without significant output disturbance. this device is capable of delivering up to 2a of output current (pvin = 2.8v, v out = 3.3v) and provides excellent efficiency due to its fully synchronous 4-switch architecture. no-load quiescent current of only 45a also optimizes efficiency under light load conditions. the isl91107ir is designed fo r standalone applications and supports 3.3v fixed output voltag es or variable output voltages with an external resist or divider. output voltages as low as 1v or as high as 5.2v are supported using an external resistor divider. the isl91107ir requires only a single inductor and very few external components. power supply solution size is minimized by its 2.5mhz switching frequency, allowing small size external components. the isl91107ir is available in a 3x4 20 ld tqfn package. features ? accepts input voltages above or below regulated output voltage ? automatic and seamless transitions between buck and boost modes ? input voltage range: 1.8v to 5.5v ? output current: up to 2a (pvin = 2.8v, v out = 3.3v) ? high efficiency: up to 96% ? 45a quiescent current maxi mizes light load efficiency ? 2.5mhz switching frequency minimizes external component size ? selectable forced pwm mode ? fully protected for short-circuit, over-temperature and undervoltage ? small 3mmx4mm tqfn package applications ? smartphones and tablet pcs ? wireless communication devices ? optical modules networking equipment figure 1. typical isl91107irtnz application figure 2. efficiency vs output current (v out =3.3v) vout fb c 2 2x22f pvin v in = 1 .8v to 5.5v vin mode en c 1 22f isl91107irtnz sgnd pgnd lx1 lx2 l 1 1h v out = 3.3v 60 65 70 75 80 85 90 95 100 0.001 0.01 0.1 1.0 3.0 efficiency (%) load current (a) v in = 2.5v v in = 2.7v v in = 3.6v v in = 3v v in = 4.2v
isl91107ir fn8687 rev 0.00 page 2 of 13 march 2, 2015 block diagram osc error ? amp pvin pwm control pvin monitor lx1 v ref ref r e v e r s e ? c u r r e n t vout lx2 gate drivers & anti- shoot thru vin thermal shutdown current detect vout monitor en fb pgnd sgnd en en en en en en vout clamp voltage prog. en soft discharge mode + + - + - - pvin en vin mode vout pgnd fb lx1 lx2 en en en en osc error amp voltage prog. vout monitor current detect vout clamp pvin monitor thermal shutdown gate drivers and anti- shoot-thru pwm control en soft discharge reverse current sgnd v ref en en ref
isl91107ir fn8687 rev 0.00 page 3 of 13 march 2, 2015 pin configuration isl91107ir (20 ld tqfn) top view 16 15 14 13 12 11 20 19 18 17 7 8 9 10 1 2 3 4 5 6 lx2 lx2 pgnd pgnd lx1 lx1 fb sgnd mode en vin nc vout vout vout vout pvin pvin pvin pvin thermal pad pin descriptions pin # pin names description 7, 8, 9, 10 pvin power input. range: 1.8v to 5.5v. connect 22f capacitor to pgnd. 12 vin supply input. range: 1.8v to 5.5v. 5, 6 lx1 inductor connection, input side. 13 en logic input for enable. drive high to enable device, low to disable. do not leave this pin floating 3, 4 pgnd power ground for high switching current. 14 mode logic input, high for auto pfm mode. low for forced pwm operation. do not leave this pin floating 1, 2 lx2 inductor connection, output side. 15 sgnd analog ground pin 17, 18, 19, 20 vout buck-boost output. connect 2x22f capacitor to pgnd. 16 fb voltage feedback pin. - epad thermal pad. connect to pgnd ordering information part number ( notes 1 , 2 , 3 )part marking vout (v) temp range (c) package (rohs compliant) pkg. dwg. # isl91107irtnz ( note 1 ) 107n 3.3 -40 to +85 20 ld tqfn l20.3x4a isl91107irtaz ( note 1 ) 107a adj -40 to +85 20 ld tqfn l20.3x4a isl91107irn-evz evaluation board for isl91107irtnz for 3.3 voltage output ISL91107IRA-EVZ evaluation board for isl91107irtaz for adj voltage output notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see product information page for isl91107ir . for more information on msl, please see tech brief tb363 .
isl91107ir fn8687 rev 0.00 page 4 of 13 march 2, 2015 absolute maximum rating s thermal information pvin, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v lx1, lx2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v sgnd, pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 250v latch-up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 3x4mm tqfn package ( notes 4 , 5 ). . . . . . 41 5.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage (v in ) range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 5.5v load current (i out ) range (dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 2a caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. analog specifications v in = pvin = en = 3.6v, v out = 3.3v, l 1 = 1h, c 1 = 1x22f, c 2 = 2x22f, t a = +25c. boldface limits apply across the recommended operating temperature range, - 40c to +85c and input voltage range (1.8v to 5.5v). symbol parameter test conditions min ( note 6 )typ max ( note 6 )units power supply vin input voltage range 1.8 5.5 v v uvlo v in undervoltage lockout threshold rising 1.75 1.795 v falling 1.60 1.71 v i vin v in supply current pfm mode, no external load on v out , no switching, v in 5v 45 60 a pfm mode, no external load on v out , with switching 60 i sd v in supply current, shutdown en = sgnd, v in 5v 0.05 0.6 a output voltage regulation vout output voltage accuracy i out = 1ma, pwm mode -2 +2 % i out = 1ma, pfm mode -3 +4 % vfb feedback voltage for adjustable version only 0.788 0.8 0.812 v ? vout/ ? vin line regulation, pwm mode i out = 500ma, mode = sgnd, v in step from 2.3v to 5.5v 0.005 mv/mv ? vout/ ? iout load regulation, pwm mode v in = 3.7v, mode = sgnd, i out step from 0ma to 500ma 0.005 mv/ma ? vout/ ? vin line regulation, pfm mode i out = 100ma, mode = v in , v in step from 2.3v to 5.5v 12.5 mv/v ? vout/ ? iout load regulation, pfm mode v in = 3.7v, mode = v in , i out step from 0ma to 100ma 0.4 mv/ma v clamp output voltage clamp rising 5.35 5.85 v v clamp _hs output voltage clamp hysteresis 400 mv dc/dc switching specifications f sw oscillator frequency 2.5 v in 5v 2.25 2.5 2.75 mhz t onmin minimum on time 80 ns i pfetleak lx1 pin leakage current -0.1 0.1 a i nfetleak lx2 pin leakage current -0.1 0.1 a
isl91107ir fn8687 rev 0.00 page 5 of 13 march 2, 2015 soft-start and soft discharge t ss soft-start time time from when en signal asserts to when output voltage ramp starts. 1ms time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in buck mode. v in = 4v, i out = 200ma 1ms time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in boost mode. v in = 2v, i out = 200ma 2ms r dischg v out soft-discharge on-resistance v in = 3.6v, en < v il 35 power mosfet r dson_p p-channel mosfet on-resistance v in = 3.6v 55 m r dson_n n-channel mosfet on-resistance v in = 3.6v 47 m i pk_lmt p-channel mosfet peak current limit v in = 3.6v 3.8 4.1 4.8 a pfm/pwm transition load current threshold, pfm to pwm v in = 3v, v out = 3.3v 375 ma load current threshold, pwm to pfm v in = 3v, v out = 3.3v 300 ma thermal shutdown thermal shutdown 150 c thermal shutdown hysteresis 30 c logic inputs i leak input leakage 0.05 0.1 a v ih input high voltage 1.4 v v il input low voltage 0.4 v note: 6. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. analog specifications v in = pvin = en = 3.6v, v out = 3.3v, l 1 = 1h, c 1 = 1x22f, c 2 = 2x22f, t a = +25c. boldface limits apply across the recommended operating temperat ure range, -40c to +85c and input voltage range (1.8v to 5.5v). (continued) symbol parameter test conditions min ( note 6 )typ max ( note 6 )units
isl91107ir fn8687 rev 0.00 page 6 of 13 march 2, 2015 typical performance curves unless otherwise noted, operating conditions are: t a = +25c, v in = en = 3.6v, l = 1h, c 1 = 22f, c 2 = 2x22f, v out = 3.3v, i out = 0a to 2a. figure 3. quiescent current vs input voltage (mode = high, v out = 3.3v) figure 4. quiescent current vs input voltage (mode = low, v out = 3.3v) figure 5. switching frequency vs input voltage figure 6. mosfet on-resistance vs input voltage figure 7. light-load efficiency vs input voltage (v out =3.3v) figure 8. output voltage vs load current 6 0 62 64 66 68 70 72 74 76 78 80 2.0 2 .5 3.0 3.5 4.0 4.5 5.0 5.5 t a = +85c t a = +25c v in (v) i q (a) t a = -40c 0 2 4 6 8 10 12 14 16 18 1.5 2.5 3.5 4.5 5.5 t a = -40c t a = +85c t a = +25c v in (v) i q (ma) 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 1.5 2.5 3.5 4.5 5.5 f sw ,t a = -40c v in (v) f sw ,t a = +25c f sw ,t a = +85c oscillator frequency (mhz) 30 40 50 60 70 80 90 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 mosfet on-resistance (m) v in (v) p-channel mosfet n-channel mosfet 75 80 85 90 95 100 1.5 2.5 3.5 4.5 5.5 v in (v) load = 100ma load = 10ma load = 1ma efficiency (%) 3.260 3.265 3.270 3.275 3.280 3.285 3.290 3.295 3.300 1 10 100 1000 v in = 3.3v load current (ma) v out (v) v in = 4.2v v in = 3.8v
isl91107ir fn8687 rev 0.00 page 7 of 13 march 2, 2015 figure 9. efficiency vs load current (v out = 2v) figure 10. supply current (switching) (v out = 5v) figure 11. efficiency vs lo ad current (mode = low, v out =3.3v) figure 12. output voltage vs load current (mode = low, v out = 3.265v) figure 13. maximum output current vs input voltage (v out =3.3v) figure 14. pfm<->pwm tran sition thresholds vs v in (v out =3.3v) typical performance curves unless otherwise noted, operating conditions are: t a = +25c, v in = en = 3.6v, l = 1h, c 1 = 22f, c 2 = 2x22f, v out = 3.3v, i out = 0a to 2a. (continued) 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 v in = 1.8v v in = 5v v in = 3.8v v in = 3v v in = 2.5v load current (ma) efficiency (%) 40 60 80 100 120 140 160 180 123456 v in (v) i q (a) 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 v in = 3v v in = 3.3v v in = 3.8v v in = 4.2v load current (ma) efficiency (%) 3.250 3.255 3.260 3.265 3.270 3.275 3.280 1 10 100 1000 load current (ma) v out (v) v in = 4.2v v in = 3v v in = 3.8v v in = 3.3v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.5 2.5 3.5 4.5 5.5 max i out , t a = +85c max i out , t a = +25c v in (v) maximum output current (a) 0 50 100 150 200 250 300 350 400 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 load current (ma) v in (v) pfm->pwm pwm->pfm
isl91107ir fn8687 rev 0.00 page 8 of 13 march 2, 2015 figure 15. efficiency vs output current (v out =5v) figure 16. 0a to 1a load transient, v out = 3.3v figure 17. 0a to 1a load transient, v out = 3.3v figure 18. 0a to 1a load transient, v in = 3v, v out = 5v figure 19. 0a to 2a load transient, v in = 3.6v, v out = 5v typical performance curves unless otherwise noted, operating conditions are: t a = +25c, v in = en = 3.6v, l = 1h, c 1 = 22f, c 2 = 2x22f, v out = 3.3v, i out = 0a to 2a. (continued) 70 75 80 85 90 95 100 0.001 0.01 0.1 1.0 3.0 v in = 3.6v v in = 3v v in = 3.3v load current (a) efficiency (%) v in = 4.2v v in = 4.5v v in (1v/div) v out (ac, 50mv/div) load (1a/div) 100s/div v in (1v/div) load (1a/div) 100s/div v out (ac, 50mv/div) v in (1v/div) v out (ac , 200mv/div) load (1a/div) 100 s/div v in (1v/div) v in (1v/div) v out (ac, 500mv/div) load (1a/div) 100s/div
isl91107ir fn8687 rev 0.00 page 9 of 13 march 2, 2015 functional description functional overview refer to the ? block diagram ? on page 2 . the isl91107ir implements a complete buck-boost switching regulator with pwm controller, internal switches, references, protection circuitry and control inputs. the pwm controller automatically switches between buck and boost modes as necessary to maintain a steady output voltage with changing input voltages and dynamic external loads. internal supply and references referring to the ? block diagram ? on page 2 , the isl91107ir provides two power input pins. the pvin pin supplies input power to the dc/dc converter, while the vin pin provides operating voltage source required for stable v ref generation. separate ground pins (sgnd and pgnd) are provided to avoid problems caused by ground shift due to the high switching currents. enable input a master enable pin en allows the device to be enabled. driving en low invokes a power-down mode, where most internal device functions are disabled. soft discharge when the device is disabled by driving en low, an internal resistor between vout and sgnd is activated. this internal resistor has a typical resistance of 35 . por sequence and soft-start bringing the en pin high allows the device to power-up. a number of events occur during the start-up sequence. the internal voltage reference powers up and stabilizes. the device then starts to operate. there is a 1ms (typical) delay between assertion of the en pin and the start of the switching regulator soft-start ramp. the soft-start feature minimizes output voltage overshoot and input inrush currents. during soft -start, the reference voltage is ramped to provide a ramping v out voltage. while output voltage is lower than approximately 20% of the target output voltage, switching frequency is reduced to a fraction of the normal switching frequency to aid in producing low duty cycles necessary to avoid input inrush current spikes. once the output voltage exceeds 20% of the target voltag e, the switching frequency is increased to its nominal value. when the target output voltage is higher than the input voltage, there will be a transi tion from buck mode to boost mode during the soft-start sequence. at the ti me of this transition, the ramp rate of the reference voltage is decreased, such that the output voltage slew rate is decreased. this provides a slower output voltage slew rate. the v out ramp time is not constant for all operating conditions. soft-start into boost mode will take longer than soft-start into buck mode. the total soft-start time into buck operating mode is typically 2ms, whereas the typical soft-start time into boost mode operating mode is typically 3ms. increasing the load current will increase these typical soft-start times. overcurrent protection the isl91107ir provides short-circuit protection by monitoring the fb voltage. when fb voltage is sensed to be lower than a certain threshold, the pwm oscillator frequency is reduced in order to protect the device from damage. the p-channel mosfet peak current limit remains active during this state. undervoltage lockout the undervoltage lockout (uvlo) feature prevents abnormal operation in the event that the supply voltage is too low to guarantee proper operation. when the v in voltage falls below the uvlo threshold, the re gulator is disabled. figure 20. 3.6v to 3v li ne transient response, v out = 3.3v, load = 1.5a figure 21. start-up with v in = 4v, r load = 1.5a, v out = 3.3v typical performance curves unless otherwise noted, operating conditions are: t a = +25c, v in = en = 3.6v, l = 1h, c 1 = 22f, c 2 = 2x22f, v out = 3.3v, i out = 0a to 2a. (continued) v out (50mv/div) v in (1v/div) 1ms/div v out (1v/div) v in (2v/div) inductor current (500ma/div) en (2v/div) 1 ms/div
isl91107ir fn8687 rev 0.00 page 10 of 13 march 2, 2015 thermal shutdown a built-in thermal protection feature protects the isl91107ir if the die temperature reaches +150c (typical). at this die temperature, the regulator is completely shut down. the die temperature continues to be moni tored in this thermal-shutdown mode. when the die temperature falls to +120c (typical), the device will resume normal operation. when exiting thermal shutdown, th e isl91107ir will execute its soft-start sequence. buck-boost conversion topology the isl91107ir operates in either buck or boost mode. when operating in conditions where v in is close to v out , the isl91107ir alternates between buck and boost mode as necessary to provide a regulated output voltage. figure 22 shows a simplified diagram of the internal switches and external inductor. pwm operation in buck pwm mode, switch d is continuously closed and switch c is continuously open. switches a and b operate as a synchronous buck converter when in this mode. in boost pwm mode, switch a remains closed and switch b remains open. switches c and d operate as a synchronous boost converter when in this mode. pfm operation during pfm operation in buck mode, switch d is continuously closed and switch c is continuously open. switches a and b operate in discontinuous mode during pfm operation. during pfm operation in boost mode, the isl91107ir closes switch a and switch c to ramp up the current in the inductor. when the inductor current reaches a certain threshold, the device turns off switches a and c, then turns on switches b and d. with switches b and d closed, output voltage increases as the inductor current ramps down. in most operating conditions, th ere will be multiple pfm pulses to charge up the output capacito r. these pulses continue until v out has achieved the upper thre shold of the pfm hysteretic controller. switching then stops and remains stopped until v out decays to the lower threshold of the hysteretic pfm controller. operation with v in close to v out when the output voltage is close to the input voltage, the isl91107ir will rapidly and smoothly switch from boost-to-buck mode as needed to maintain the regulated output voltage. this behavior provides excellent efficiency and very low output voltage ripple. applications information component selection the fixed output versions of the isl91107ir require only three external power components to implement the buck boost converter: an inductor, an input capacitor and an output capacitor. the adjustable isl91107ir version requires three additional components to program the output voltage. two external resistors program the output voltage and a small capacitor is added to improve stability and response. setting and controlling the output voltage of the isl91107ir (adjustable output version) can be accomplished by selecting the external resistor values. equation 1 can be used to derive the r 1 and r 2 resistor values: when designing a pcb, include an sgnd guard band around the feedback resistor network to reduce noise and improve accuracy and stability. resistors r 1 and r 2 should be positioned close to the fb pin. inductor selection an inductor with high frequency core material (e.g., ferrite core) should be used to minimize core losses and provide good efficiency. the inductor must be able to handle the peak switching currents without saturating. a 1h inductor with 4.1a saturation current rating is recommended. select an inductor with low dcr to provide good figure 22. buck-boost topology pvin vout switch a switch d switch b switch c lx1 lx2 l 1 figure 23. typical application v out = 3.3v vout fb c 2 2x22f r 1 r 2 187k 60.4k pvin v in = vin mode en c 1 22f isl91107irtaz sgnd pgnd lx1 lx2 l 1 1h c 4 22pf 1.8v to 5.5v v out 0.8v 1 r 1 r 2 ------ - + ?? ?? ?? ? = (eq. 1)
isl91107ir fn8687 rev 0.00 page 11 of 13 march 2, 2015 efficiency. in applications where radiated noise must be minimized, a toroidal or shielded inductor can be used. pvin and v out capacitor selection the input and output capacitors should be ceramic x5r type with low esl and esr. the recommended input capacitor value is 22f, as this would provide adequate rms current to minimize the input voltage ripple. a minimum of 10f is required to maintain full functionality of the part. the recommended output capacitor is 2x22f, 10v, x5r. note that the effective value of a ceramic capacitor derates with dc voltage bias across it. this dera ting may be up to 70% of the rated capacitance. refer to the capacitor datash eet to ensure the combined effective output capacitance is at least 14f for proper operation over the entire recommended load current range. low output capacitance may lead to large output voltage drop during load transient or unst able operation. recommended pcb layout correct pcb layout is critical for proper operation of the isl91107ir. the following are some general guidelines for the recommended layout: 1. the input and output capacitors should be positioned as close to the ic as possible. 2. the ground connections of the input and output capacitors should be kept as short as possible. the objective is to minimize the current loop between the ground pads of the input and output capacitors and the pgnd pins of the ic. use vias, if required, to take advantage of a pcb ground layer underneath the regulator. 3. the analog ground pin (sgnd) should be connected to a large/low-noise ground plane on the top or an intermediate layer on the pcb, away from the switching current path of pgnd. this ensures a low noise signal ground reference. 4. minimize the trace lengths on the feedback loop to avoid switching noise pick-up. vias should be avoided on the feedback loop to minimize the effect of board parasitic, particularly during load transients. 5. the lx1 and lx2 traces should be short and must be routed on the same layer as the ic. table 1. inductor vendor information manufacturer mfr p/n description cyntec pife32251b-1r0ms 1h, 3.2x2.5x1.2mm toko dfe322512c 1h, 3.2x2.5x1.2mm table 2. capacitor vendor information manufacturer pn description murata grm188r61a226me15d 22f, 0603, 10v, x5r tdk c1608x5r1a226m080ac 22f, 0603, 10v, x5r figure 24. recommended layout
fn8687 rev 0.00 page 12 of 13 march 2, 2015 isl91107ir intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2015. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 2, 2015 fn8687.0 initial release.
isl91107ir fn8687 rev 0.00 page 13 of 13 march 2, 2015 package outline drawing l20.3x4a 20 lead thin quad flat no-lead plastic package rev 0, 6/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view jedec reference drawi ng: mo-220vegd-nji. 7. 3.00 4.00 a b (4x) 0.10 6 pin 1 index area c 0 . 2 ref 0 . 05 max. 0 . 00 min. 16 1 0.10 c 0.08 c seating plane pin #1 6 0.10 -0.07 a mc b 4 index area 11 6 -0.15 1.65 +0.10 20x 0.40+/-0.10 2.65 +/0.10 16x 0.50 20x 0.25 +0.05 -0.15 0.05 m c (20x 0.25) (20x 0.60) (16x 0.50) (1.65) (2.80) (2.65) (3.80) see 0.80 max c a a 17 10 7 20 detail "x" view "a-a"

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